The present disclosure relates to a method for constructing an electrical circuit comprising at least one semiconductor chip, to an electrical circuit comprising at least one semiconductor chip, and to a sensor module comprising the electrical circuit.
So-called wafer level packaging is used in chip construction and connection technology. In this case, the individual packaging processes are carried out on the silicon wafer or on an arrangement in the wafer format.
U.S. Pat. No. 3,579,056 A1 describes a method for producing a semiconductor device, wherein semiconductor components are fitted onto a carrier and are enclosed by a polyurethane layer. Afterward, the carrier is removed and conductors for the semiconductor components are fitted.